Low resistance metals have been adopted for use in gate electrodes to enhance operational speed as the size of such transistors is scaled-down (i.e., reduced). Tungsten is a suitable material for use in such low resistance gates because the tungsten may not be transformed in a subsequent thermal process, and the diffusion of tungsten through insulating layers may be less. Compared with conventional polycide gate electrodes, polymetal gates including tungsten may have low resistivity and be less affected by line-width.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional transistor and a method for fabricating the same. Referring to FIG. 1, a device isolation layer 12 is formed on a semiconductor substrate 10 to define an active region. In a conventional Dynamic Random Access Memory (DRAM) device, the device isolation layer 12 defines a plurality of isolated active regions, and the active regions are arranged over the length and width of the substrate 10. A gate insulating layer 16 is on an upper portion of the active region.
A gate electrode 28 is on the gate insulating layer 16 and includes a silicon layer 18 and a tungsten layer 22. An adhesion layer 20 formed of a metal nitride layer can be between the silicon layer 18 and the tungsten layer 22. The silicon layer 18 may be polysilicon or amorphous silicon. The adhesion layer 20 enhances adhesion between silicon and tungsten, and may also function as an ohmic layer. A capping layer 24 is formed on an upper portion of the tungsten layer 22.
Referring to FIG. 2, the gate electrode 28 is formed by patterning the silicon layer, the adhesion layer 20, the tungsten layer 22, and the capping layer 24. When the silicon layer 18 is etched, there is a possibility that a surface of the gate electrode 28 may be adversely effected. A thermal oxidation process may be used to cure the surface defects on the silicon layer created by the etch. The thermal oxidation process may cause a sidewall of the silicon layer 18 to be oxidized to form a thermal oxide layer 26 thereon. Oxidizing the gate electrode 28 may cause an increase in the parasitic capacitance and resistance associated with the transistor.
Referring to FIG. 3, a LDD layer (not shown) in the substrate at both sides of the gate electrode 28 is formed by curing the defects and applying an ion implantation process. Then, a sidewall spacer 30 is formed on sidewalls of the gate electrode 28 and, impurities are implanted into the substrate to form high concentration source/drain (not shown).
In the case of a polymetal gate electrode including a silicon layer and a metal layer in a transistor fabrication process, tungsten may be used to replace tungsten silicide or a multi-layered structure including an adhesion layer and a tungsten layer.